Kota Naga Srinivasarao Batta

Assistant Professor

Department of Electronics & communication Engineering

National Institute of Technology, Warangal - 506004, Telangana, INDIA

: srinu.bkn@nitw.ac.in

: 9800296596

Interests: VLSI architectures for image and video processing, Embedded systems design, IOT, System-on-Chip design.

Educational Details
  • Ph.D(2017): Electronics and Communications Engineering, Indian Institute of Technology ,Kharagpur-INDIA.
  • M.Tech(2008): Visual Information and Embedded Systems, Indian Institute of Technology ,Kharagpur-INDIA.
  • B.Tech.(2002):Electronics and Communications Engineering,  Nagarjuna university, Andhrapradesh, INDIA.
Work Experience
  • Assistant  Professor, From April 2018 to till date , Dept. of ECE, National Institute of Technology, Warangal, Telangana-INDIA.
  • Professor From August 2017 to March 2018 , Dept. of ECE, Gudlavalleru Engineering College, Gudlavalleru, INDIA.
  • Research Scholar From  January 2013 to 2017, Dept. of ECE, Indian Institute of Technology ,Kharagpur-INDIA.
  • Associate Professor, From  July 2008  to December 2012, Dept. of ECE, Gudlavalleru Engineering College, Gudlavalleru, INDIA..
  • Assistant  Professor, From  September 2002 to  June 2008 , Dept. of ECE, Gudlavalleru Engineering College, Gudlavalleru, INDIA.

Course Taught Previously

  1. Electronic Devices and Circuits-I
  2. Electronic Devices and Circuits-II
  3. Switching Theory & Logic Design
  4. Microprocessors and Microcontrollers
  5. Advanced Microcontrollers
  6. Microcontrollers and Applications
  7. CPLD and FPGA Architectures and Applications
  8. Embedded System Design
  9. Basic Electronics

Publications

 Book

  • Indrajit Chakrabarti, B.K.N. Srinivasarao and Sumit Kumar Chatterjee, "Motion Estimation for Video Coding : Efficient Algorithms and Architectures", published in Studies in Computational Intelligence and Complexity, Springer, vol.590, 2015.

Journals

  1. B.K.N. Srinivasarao, and I. Chakrabarti , "VLSI Architecture for Enhanced Approximate Message Passing Algorithm",  IEEE Transactions on Circuit Systems for Video Technology (Early Access) DOI: 10.1109/TCSVT.2019.2943363, Sep 2019.
  2. B. K. N. Srinivasarao, Vinay Chakravarthi.G, Subrahmanyam. M, and I. Chakrabarti, "A novel Framework for Compressed Sensing based Scalable Video Coding", Signal Processing: Image Communication, Elsevier, vol:57, pp.183-196, 2017.
  3. B.K.N. Srinivasarao, I. Chakrabarti and Mohammad Nawaz Ahmad, "High-speed lowpower very-large-scale integration architecture for dual-standard deblocking filter", IET journal of Circuits, Devices & Systems, vol. 9, no. 5, pp. 377-383, 2015.
  4.  B. K. N. Srinivasarao and I. Chakrabarti, "Hardware Implementation of In-Band Motion Compensated Temporal Filtering", Annual Technical Volume of ETEB, Institute of Engineers (India), Theme: Design of Circuits and Systems for Signal, Image and Video Processing, vol. 1, pp. 41-51, 2016.
  5. B. K. N. Srinivasarao and I. Chakrabarti, "High Speed and Memory Efficient VLSI Architecture for 3-D Inverse DWT", Annual Technical Volume of ETEB, Institute of Engineers (India), Theme: Design of Circuits and Systems for Signal, Image and Video Processing, vol. 1, pp. 52-59, 2016.
  6. P.Ravi Sankar, B.K.N. Srinivasarao, "Parallel Architecture for Implementation of Contrast Limited Adaptive Histogram Equalization", International Journal Of Advanced Engineering Sciences And Technologies, vol. 10, no. 1, pp. 047-051, 2011.
  7. G. Siva Kumar, B.K.N. Srinivasarao, "Design of Area and Power Efficient Floatingpoint Co-processor", International Journal Of Advanced Engineering Sciences And Technologies, vol. 10, no. 2, pp. 249-251, 2011.

Conferences

  1. S. N. Karishma, B. K. N. Srinivasarao, and I. Chakrabarti,and Chandra Prakash, "Hardware/software co-simulation of entropy coder for compressive sensing based scalable video codec system", in Proc. of IEEE International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), March 2017.
  2. S. N. Karishma, B. K. N. Srinivasarao, and I. Chakrabarti,"Compressive Sensing based Scalable Video Coding for Space Applications," in Proc. of IEEE 22nd National Conference on Communication (NCC-2016), 4-6 March 2016, Bangalore, India
  3. B. K. N. Srinivasarao and I. Chakrabarti, "High performance VLSI architecture for 3- D discrete wavelet transform," in proc. of IEEE 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp.1-4, 25-27 April 2016, Hsinchu, Taiwan.
  4. S. N. Karishma, B. K. N. Srinivasarao, and Indrajit Chakrabarti, "Scalable Video Coding based Method for Compressing Satellite and Space-borne Data", in Proc. of 1 st Space Development Network Conference (SDN-2016), 9-10 January 2016, Bangalore, India.
  5. B.K.N. Srinivasarao, A. Mondal and I. Chakrabarti, "FPGA implementation of InBand Motion Compensated Temporal Filtering for scalable Video coding", in Proc. of IEEE International Conference on VLSI and Signal Processing (ICVSP-2014), Dec 10-12, 2014, IIT Kharagpur, India.
  6. B.K.N. Srinivasarao and I. Chakrabarti, "A Parallel Architecture for Successive Elimination Block Matching Algorithm", in Proc. of IEEE 6 th Indian Conference on Comp. Vision, Graphics and Image Proc. (ICVGIP-2008), pp. 226-231, Dec. 16-19, 2008, Bhubaneswar, India.
  7. B.K.N. Srinivasarao and I. Chakrabarti, "A parallel architectural implementation of the fast three step search algorithm for block motion estimation", in Proc. of IEEE 5 th International Multi-Conference on Systems, Signals and Devices, 2008. (SSD 2008), pp. 1-6, 20-22 July 2008, Amman, Jordan.
  8. B.K.N. Srinivasarao, S.K. Chatterjee and I. Chakrabarti, "Low Power VLSI Architecture for a Fast Three Step Search Algorithm", in Proc. of International Conference on RF and Signal Processing Sys.(RSPS-2008), pp. 286-291, Feb. 1-2, 2008, Vijayawada, India.

PHDs Supervised

 

Workshops/Conferences

  1.  Organized summer training on VLSI design for III B.Tech, ECE students at IIT kaharagpur during 1-30 may, 2015. 
  2. Organized Laboratory session on "Design of VLSI architecture for Image and video processing applications" in One-Week ISTE STTP for Coordinators on CMOS, Mixed Signal and Radio frequency VLSI Design workshop during 19th to 23rd September 2016. (Participants are faculty members from 210 engineering colleges throughout India)

Projects

 

Awards and Honors

 

Additional Responsibility

  • Institute Level 
    • Faculty Incharge, Telecom Centre, NITW
  • Department Level
    • Time table cordinator
    • Lab Incahrge, Electronic circuits Lab