Academic Qualifications:

Ph.D. in Microelectronics and VLSI, Dept. of E&CE, Indian Institute of Technology Roorkee (2010 - 2014) (Defended in July 2015, Ph.D. awarded in October 2015) Thesis: "Design and Analysis of Vertical Nanowire CMOS Devices and Circuits," under supervision of Dr. S. K. Manhas and Dr. A. Bulusu.

Master of Technology (M. Tech.) in Semiconductor Devices and VLSI Technology, Dept. of E&CE, Indian Institute of Technology Roorkee (2008-2010) 

B. E. in Electronics and Communication Engineering, MVSR Engineering College, Hyderabad (2003-2007) 

Work Experience:

Marri Laxman Reddy Institute of Technology & Management, Hyderabad  (Oct. 2015 - April 2018) worked as Asst. Prof., Dept. of ECE

Indian Institute of Technology Roorkee, Roorkee (Aug. 2009 - June 2010) and (Aug. 2010 - May 2014) worked as lab instructor (Teaching assistantship workload) for B. Tech/M. Tech students, handled Solid State Devices, VLSI Design, Digital Hardware and Basic Electronics Laboratory courses. .

Cognizant Technology Solutions India Pvt. Ltd., Chennai  (Nov., 2007 - Jul., 2008) worked as Programmer Analyst Trainee for the development of web based application for Emdeon (client) health care product on Java platform (Core Java, J2EE and Javascripts) 

Technical Skills:

Device Simulation tools       :      Synopsys (Sentaurus) /Visual (Genius) TCAD

Circuit Simulation tools       :       HSPICE (along with VerilogA interface), SYMICA DE

FPGA Design Tools                :       Xilinx ISE

Embedded Design                  :        Keil, Proteus (for 8051, 8-bit MicroController based design), Arduino IDE, Raspberry Pi

Learning Management Tools: Moodle, Bodhitree

Programming Languages    :       VerilogA, HDL, MATLAB, C, CPP, CoreJava, Adv.Java.

Characterization of MOS devices on wafer using parametric analyzer (Keitheley 4200) and probe station.

 PG Dissertations guided: 9

9. G. Nikitha Raj, "UVM Based Verification of IP Blocks", M.Tech Dissertation, 2022. (Work done during internship at AMD, Bengaluru).

8. Y. Sai Rakesh, "Multi Voltage Timing Verification", M.Tech Dissertation, 2022. (Work done during internship at Nvidia, Hyderabad).

7. I. Kousalya, "Real-time SoC Block-level Implementation in Physical Design", M.Tech Dissertation, 2021. (Work done during internship at Mediatek, Bengaluru).

6. M. Uday Kumar, " Interface Timeout to Achieve Deterministic Regression Run-Time", M.Tech Dissertation, 2021. (Work done during internship at Qualcomm, Bengaluru).

5. K. Himanshu, " Reliability Verification and Signoff checks at Partition level in ASIC Physical Design", M.Tech Dissertation, 2021. (Work done during internship at Intel, Bengaluru).

4. D. Nikita, "Zero Temperature Coefficient Voltage and Current Generator", M.Tech Dissertation, 2020.

3. Neha Karna, "Analysis of Area, Timing, Power and Speed Considering Two Different Synthesis Corners at Lower Technology", M.Tech Dissertation, 2020. (Work done during internship at AMD, Hyderabad)

2. M. Krishna, "Power Optimization Using Structural Design Techniques in Back end at Lower Technology", M.Tech Dissertation, 2019. (Work done during internship at Intel, Bengaluru)

1. M. Tushar, "Verification of Convolution on FPGAs", M.Tech Dissertation, 2019. (Work done during internship at AMD, Hyderabad)

UG major projects guided:  @NITW - 5

                                               @MLRITM - 9

Professional Memberships:

IEEE  (ID: 91120037) Member (Electron Devices and Circuit & System society) from 2010, Robotics and Automation Society from 2020.

IETE (ID: 501796) Member from 2020.

NIT Warangal

        PG courses :          Microchip Fabrication Techniques - July-Nov. 2018, July - Nov. 2019,  Sept. - Dec. 2020, Sept. - Dec. 2021

                                       Modern/Advanced Computer Architecture: Jan. - May 2021, Jan. - May 2022

                                       VLSI Design (Physics): Sept. - Dec. 2021

                                       Reliability of Devices and Circuits: Dec. 2019 to Apr. 2020

                                       Testing and Testability  - Dec. 2018 to Apr. 2019

                                       Seminar I/C: July-Nov. 2018, July - Nov. 2019

           UG courses :       Basic Electronics Engineering - July - Nov. 2018, Dec. 2018 - Apr. 2019, July - Nov. 2019, Dec. 2019 - Apr. 2020,

                                                                                                                               Dec. 2020 - Mar.2021, Apr. - July 2021

                                      Digital System Design Lab: Dec. 2018 - Apr. 2019, Dec. 2019 - Apr. 2020,  Jan. - May 2021  

                                      EI & DSP Lab: July - Nov. 2019                                                  

                                      Microcontrollers Lab: Sept. - Dec. 2020, Sept. - Dec. 2021

Marri Laxman Reddy Institute of Technology & Management, Hyderabad  (Oct. 2015 - April 2018)  

PG courses :                 Sensors & Actuators  - 1 

UG courses :                 Analog Electronics - 1

                                      Digital Design through Verilog HDL - 2 

                                      VLSI Design - 2

                                      Switching Theory & Logic Design - 1

                                      Electrical Circuits - 1

 Journals

• K Sagar, S. Maheshwaram, "Performance Analysis of Sub 10nm Double Gate Circular MOSFET", Springer Silicon, Jan. 2022.
• K Sagar, S. Maheshwaram, "A novel circular double gate SOI MOSFET with raised source/drain", IOP Semicondcutor Science and Technology 36 (6), 065009, Apr. 2021.
• Om Prakash, S. Maheshwaram, Swen Beniwal, Naresh Gupta, N Singh, SK Manhas, "Impact of Time Zero Variability and BTI Reliability on SiNW FET-Based Circuits", IEEE Transactions on Device and Materials Reliability 19 (4), 741-750, Apr. 2019.
• CV SaikumarReddy, C Venkataiah, Vobulapuram Ramesh Kumar, S. Maheshwaram, N Jain, S Dasgupta, SK Manhas, "Design and Simulation of CNT Based Nano-Transistor for Greenhouse Gas Detection", in Journal of Nanoelectronics and Optoelectronics 13 (4), 593-601, Apr. 2018.
• O. Prakash, S. Maheshwaram, M. Sharma, A. Bulusu and S. K. Manhas, "Performance and Variability Analysis of SiNW 6T-SRAM Cell using Compact Model with Parasitics," in IEEE Transactions on Nanotechnology, vol. 16, no. 6, pp. 965-973, Nov. 2017.    
• O. Prakash, S. Beniwal, S. Maheshwaram, A. Bulusu, N. Singh and S. K. Manhas, "Compact NBTI Reliability Modeling in Si Nanowire MOSFETs and Effect in Circuits," in IEEE Transactions on Device and Materials Reliability, vol. 17, no. 2, pp. 404-413, June 2017.   
• G. Kaushal, H. Jeong, S. Maheshwaram, S.K. Manhas, S. Dasgupta, S.O. Jung, "Low power SRAM design for 14 nm GAA Si-nanowire technology," Microelectronics Journal, vol. 46, no. 12, Part A, pp. 1239-1247, Dec. 2015.
• G. Kaushal, S. K. Manhas, S. Maheshwaram, B. Anand, S. Dasgupta and N. Singh, "Novel Design Methodology Using L_EXT Sizing in Nanowire CMOS Logic," in IEEE Transactions on Nanotechnology, vol. 13, no. 4, pp. 650-658, July 2014.
• R. Shankar, G. Kaushal, S. Maheshwaram, S. Dasgupta and S. K. Manhas, "A Degradation Model of Double Gate and Gate-All-Around MOSFETs With Interface Trapped Charges Including Effects of Channel Mobile Charge Carriers," in IEEE Transactions on Device and Materials Reliability, vol. 14, no. 2, pp. 689-697, June 2014.
• A. Pandey, S. Raycha, S. Maheshwaram, S.K. Manhas, S. Dasgupta, A.K. Saxena, and B. Anand, "Effect of Load Capacitance and Input Transition Time on FinFET Inverter Capacitances," IEEE Transactions on Electron Devices, vol.61, no.1, pp.30-36, Jan. 2014.
• S. Maheshwaram, S.K. Manhas, G. Kaushal, B. Anand and N. Singh, "Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis," IEEE Transactions on Electron Devices, vol.60, no.9, pp.2943-2950, Sept. 2013.
• GauravKaushal, S.K. Manhas, S. Maheshwaram, and S. Dasgupta "Impact of Series Resistance on Si Nanowire MOSFET Performance" Springer Journal of Computational Electronics, no. 13, pp. 449-458, Mar. 2013.
• GauravKaushal, S.K. Manhas, S. Maheshwaram, S. Dasgupta, B. Anand, and N. Singh, "Tuning Source/Drain Extension Profile for Current Matching in Nanowire CMOS Logic" in IEEE Transactions on Nanotechnology, vol. 11, no. 5, pp. 1033-1039, Sep. 2012.
• S. Maheshwaram, S.K. Manhas, G. Kaushal, B. Anand, N. Singh, "Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform," IEEE Electron Device Letters, vol.33, no.7, pp.934-936, Jul. 2012.
• GauravKaushal, S. S. Rathod, S. Maheshwaram, S. K. Manhas, A. K. Saxena, and S. Dasgupta, "Radiation Effects in Si-NW GAA FET and CMOS Inverter: A TCAD Simulation Study" in IEEE Transactions on Electron Devices, vol. 59, no. 5, pp. 1563-1566, May 2012.
• S. Maheshwaram, S.K. Manhas, G. Kaushal, B. Anand, N. Singh, "Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS," IEEE Electron Device Letters, vol.32, no.8, pp.1011-1013, Aug. 2011.

 Conference

• S. Babu, B. S. Pragathi, U. Chinthala and S. Maheshwaram, "Subject Tracking with Camera Movement Using Single Board Computer," in Proc. IEEE-HYDCON, pp. 1-6, 2020.
• V. V. Reddy, T. Dhyanchand, G. V. Krishna and S. Maheshwaram, "Virtual Mouse Control Using Colored Finger Tips and Hand Gesture Recognition," in Proc. IEEE-HYDCON, pp. 1-5, 2020.
• S. Maheshwaram, Om.Prakash, M. Sharma, A. Bulusu, and S.K. Manhas, "Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance" in Proc. International Symposium on VLSI Design and Test, Springer, pp. 239-248, 2017.
• S. K. Gautam, S. Maheshwaram, S. K. Manhas, Arvind Kumar, Steven Sherman, and Sung Ho Jo, "Reduction of GIDL using Dual Work-Function Metal Gate in DRAM," in Proc, IEEE 8th International Memory Workshop (IMW) Paris, France, pp. 1-4, (2016)
• Om.Prakash, M. Sharma, S. Maheshwaram, A. Bulusu, A.K. Saxena, and S.K. Manhas, "A Unified Verilog-A Compact Model for Lateral Si Nanowire (NW) FET Incorporating Parasitics for Circuit Simulation,"in Proc. IEEE International Symposium on VLSI Design and Test (VDAT), Guwahati, India, pp. 1-6, 2016.
• O. Prakash, S. Maheshwaram, M. Sharma, A.Bulusu, A.K Saxena, and S.K. Manhas, "Lateral Silicon Nanowire Based Circuit Design Using Verilog-A Compact Model Incorporating Parasitics" accepted at 15^th International Symposium on Integrated Circuits (ISIC)-2016, Singapore.
• O. Prakash, S. Maheshwaram, M. Sharma, A.Bulusu, S.K. Manhas, A.K Saxena, "Lateral Silicon Nanowire Based Standard Cell Design for Higher Performance," in proc. 13^th IEEE Asia Pacific Conference on Circuits & Systems (APCCAS), Jeju, Korea, pp. 135-138, 2016.
• M. Sharma, S. Maheshwaram, O. Prakash, A. Bulusu, A. K. Saxena and S. K. Manhas, "Compact model for vertical silicon nanowire based device simulation and circuit design," in Proc. IEEE ISOCC, pp. 107-108, 2-5 Nov. 2015, Gyungju, South Korea.
• S. Maheshwaram, S.K. Manhas, and B. Anand, "Vertical Nanowire Transistor Based CMOS VTC Analysis," in Proc. IEEE 2nd International Conference on Emerging Electronics (ICEE), IISc Bangalore, PP. 1-4, 2014.
• G. Kaushal, S. Maheshwaram, S. Dasgupta, and S.K. Manhas, "Drive matching issues in multi gate CMOS inverter," in proc. IEEE International Conference On Signal Processing And Communication (ICSC), Noida, India, pp.349-354, 12-14 Dec. 2013.
• S. Maheshwaram, S.K. Manhas, G. Kaushal, and B. Anand, "Vertical Nanowire MOSFET Parasitic Resistance Modeling," in proc. IEEE International Conference of Electron Devices and Solid-state Circuits (EDSSC), Hong Kong, pp.1-2, 3-5 Jun. 2013.
• A. Pandey, S. Raycha, S. Maheshwaram, S. K. Manhas, S. Dasgupta, A. K. Saxena and B. Anand "FinFET Device Capacitances: Impact of Input Transition Time and Output Load," Proc. Nanoelectronics conference (INEC), Singapore, pp.393-395, 2-4 Jan. 2013.
• S. Maheshwaram, G. Kaushal, S. K. Manhas, "A High Performance Vertical Si Nanowire CMOS for Ultra High Density Circuits," in Proc. IEEE APCCAS, pp. 1219-1222, Dec. 2010, Kuala Lumpur, Malaysia.
• Sesidhar VSR Devalraju, S Maheshwaram, A Kishore, "Weather Monitoring Station", in Proc. NCIS 2007, Dept of ECE, MJCET, Hyderabad.
•  S. Maheshwaram, A. Veena, B. Swathi, B. Sarala, "CDMA wireless link achieved through Gold Codes and Modulation through FSK," at All India Seminar on "Role of Telecommunication for Betterment of Society" at Institution of Engineers, Hyderabad (2006).

•  Rudravaram Srikanth, registered as Full Time with Department of ECE, NIT Warangal, Telangana in Aug. 2021.

                         Topic: 2D material based MOSFET Design and Analysis

                          Status: Research work

•  Ravi Kothapally, registered as Full Time with Department of ECE, NIT Warangal, Telangana in Dec. 2019. He is co-supervised by Dr. V. Narendar

                       Topic: Nanowire/Nanosheet MOSFET Design and Analysis

                       Status: Research work

• Kallepelli Sagar, registered as Full Time scholar with Department of ECE, NIT Warangal, Telangana in Dec. 2018.

                       Topic: Circular Gate MOSFET Design and Analysis

                       Status: Research work

• Research Advisor to Mr. K. Nagabhushanam, registered as External Part Time with the School of Electronics  Engineering (SENSE), Vellore Institute of Technology Deemed to be University, Vellore,Tamil Nadu.
             Topic: Design of SRAM using Vertical Nanowire FET   

                      Status: First Doctoral Committee meeting held in June 2017 and completed coursework in June 2018. 

NIT Warangal

• Attended a three day workshop on "Outcome Based Education", from 7 - 9 July 2021, Organised by NITW

• Attended a one day workshop on, "SAFE tools for Online Exams", on 19th June 2021, organised by IIT Bombay.
• Attended a two day workshop on, "Bodhitree LMS", on 12th, 18th June 2021, organised by IIT Bombay.
• Organised a 10 day Faculty Development Programme on, "System Design Methodologies for Embedded, IoT, AI, & HPC using Intel FPGA", from 19th - 30th April 2021, EICT NIT Warangal, IIT Guwahati, IIITDM Jabalpur, MNIT Jaipur and NIT Patna.
• Attended a one day workshop on, "Moodle Workshop for Faculty", on 14th December 2020, organised by TEQIP III, IIT Bombay.
• Attended a one week workshop on, "Analog IC Design using Free Software Tools", from 02nd to 06th October 2020, organised by TEQIP III, IIT Hyderabad.
• Organised a one week Faculty Development Programme on " Content Preparation and Delivery for Online Mode of Teaching (CPDOMT)", from 05th to 10th October 2020, sponsored by Teaching Learning Centre, NIT Warangal. 
• Attended a one week workshop titled, "Open Source Learning Management System: Modular Object-Oriented Dynamic Learning Environment (MOODLE)", from 16-20th June 2020, AMU Aligarh.
• Attended a two day workshop titled, "4th India ESD workshop", from 26-27th February 2020, IISc Bangalore.
• Organised a Short Term Training Programme on "Machine Learning & Deep Learning for Real Time Applications" from 29th Nov. to 08th Dec. 2019, sponsored by DST, ICPS.
• Organised a one week Faculty Development Programme on "Nanoscale Devices and Circuits" from 17th to 22nd June 2019 along with E&ICT academy, NIT Warangal.
• Organised a one week Faculty Development Programme on "Advanced CMOS VLSI" from 3rd to 8th December 2018 along with E&ICT academy, NIT Warangal.
• Attended a one week Induction Training Programme  (Phase-II), from 17th to 22nd Sept. 2018, organised by TLC, NIT Warangal.
• Attended a three week Induction Training Programme  (Phase-I), from 11th to 30th June 2018, organised by TLC, NIT Warangal.

Expert Lectures Delivered:

MLRITM

• Coordinator of National level technical symposium "Valorous 2k18" held on 23-24 February 2018.
• Presented a research paper titled, "Vertical Silicon Nanowire Based Standard Cell Design for Higher Performance," in International Symposium on VLSI Design and Test (VDAT), Roorkee, India, 2017
• Coordinator of National level technical symposium "Valorous 2k17" held on 28-29 March 2017 and Annual day celebrations on 6th April 2017.
• Organised a one day FDP for ECE faculty on "Fibre Optic Sensors and Research Methodologies" by Dr. D.Dinakar, Professor and Dr. Kishore, Asst. Professor, from NIT Warangal on 16th March 2017.
• Organised a one day FDP for faculty on "Technical Paper Writing Using LaTex" by Dr.Srinivas Nallagonda on 17th March 2017.
• Organised a one day FDP for faculty on "Role of Teachers in changing times by Prof. M.L.Saikumar" on 18th March 2017.
• A One Day Workshop was conducted for the ECE faculty on "The 8051 Micro Controller and Embedded System" 6th March, 2017.
• Attended workshop on "3D Printing" at Vasavi Engineering College, Ibrahimbagh, Hyderabad, India on 21st January 2017.
• A Two Day Workshop was conducted for the students on "Embedded Systems" on 30th Dec 2016 and 6th Jan 2017.
• Presented a research paper titled "A Unified Verilog-A Compact Model for Lateral Si Nanowire (NW) FET Incorporating Parasitics for Circuit Simulation," in IEEE International Symposium on VLSI Design and Test (VDAT), Guwahati, India, 2016
• Coordinator of National level technical symposium "Valorous 2k16" held on 16-17 March 2016 and Annual day celebrations on 19th March 2016.
• Organized Faculty Development Program on "CAE & CFD" from 29-30 Nov. 2015 and the resource persons are from SIMTECH solutions, Hyderabad. 
• Organized Faculty Development Program on "VLSI System Design" on 28th Nov 2015 and the speaker is Dr. Rahul Shreshta (Asst. Prof. IIIT Hyderabad).
• Organized Faculty Development Program on "Exploring for Excellence in Education" on 26th Nov. 2015 and the speaker is Prof. M L Sai Kumar (last served as Dean - Academics at the Institute of Public Enterprise, Hyderabad).

IIT Roorkee

• Presented a research paper titled "Vertical Nanowire MOSFET Parasitic Resistance Modeling," in IEEE International Conference of Electron Devices and Solid-state Circuits (EDSSC), Hong Kong, Jun. 2013

Awards:

• Young scientist travel grant from Department of Science and Technology, Ministry of Information Technology, Govt. of India to attend IEEE EDSSC 2013, an international conference held at Hong Kong. 

Honors:

• Secretary, Robotics & Automation Society, IEEE Hyderbad Chapter from No. 2021 onwards.
• EXPERT member of the BOS (Board of Studies) PG (ES & VLSID) – Department of Electronics and Communication Engineering.
  Maturi Venkata Subba Rao Engineering College (MVSREC) from the A.Y 2021-2022
• Organized and acted as Judge in Smart India Hackathon, 2-3 March 2019, held at NIT Warangal
• Chaired at MOS- AK India 2019, held at IIT Hyderabad from 25-27 February 2019.

National Institute of Technology Warangal, Warangal (Apr. 2018  onwards)

Marri Laxman Reddy Institute of Technology & Management, Hyderabad  (Oct. 2015 - April 2018) 

Head of Department from July 2016 to Feb. 2017, during which the dept. under went NBA process and attained it for a period of 3 years.

Dean R&D (Nov. 2015-April 2018), executed the duties of R&D cell as its Dean.  I have conducted FDPs for faculty improvement, SDPs for student improvement and coordinated the college annual events (Induction of freshers, Graduation day, Technical Festival-Valorous, Annual day - Elysium). I also motivated the young faculty to register and pursue PhD, which has resulted in increase in SCI listed journals published under MLRITM affiliation.  Further, during 2016-2017 academic year I have established Robotics & Automation Research centre in dept. of ECE and helped for IoT centre in dept. of CSE.  Along with these focus has been on submission and execution of sponsored projects under DST, AICTE etc., by various doctorate faculties. I have submitted one sponsored project under FIST, DST (SR/FST/COLLEGE-/2017/81) to establish NI LabView Research centre worth 60.3 Lakhs which got rejected during review phase. 

Indian Institute of Technology Roorkee, Roorkee (July 2010 - April 2014)

High Performance Cluster Admin: From Jan. 2011 - Dec. 2014, I have been instrumental in maintaining the using X2200 Sunfire HPC (20 Nodes) with Rocks clustering software over CentOS 4.5, it is used for running atomistic simulations. Also, helped in established of Infiniband cluster in VLSI Design Lab.

System Admin.: From July 2010-Dec. 2014, I have managed the license usage of EDA and TCAD software's, and handling various system administrative works associated with the Sponsored Project Lab (MEV Group).

MEV Website Designer: From July 2010 - July 2013, I have designed and maintained the MEV group website.