Educational Details

Ph. D  : VLSI architectures for Video & Image Processing Algorithms , NIT Warangal

Thesis Title :“Development of Efficient Architectures for Motion Estimation Algorithms of Video Compression Applications”

M.Tech : Electronic Instrumentation, NIT Warangal

B.Tech: Electronics and Communication Engineering,NIT(REC) Warangal

Teaching Experience 

Research Engineer (1997-2004): Problem Oriented Research Lab,Dept. of ECE,NIT Warangal

Assistant Professor(2004-2011):Dept of ECE,NIT Warangal

Associate Professor(2012-Till Date),Dept of ECE,NIT Warangal

Industrial Experience

1.Hardware Design Engineer  (1994 - 1996): Apollo computing Labs Pvt.Ltd, Hyderabad.

2.Hardware Design Engineer ( 1996-1997): Serveen Software Systems Pvt.Ltd.Hyderabad.

Job Description:

1.Design and development of BISA-ISA-1553B  add-on card   provides three independent  configurable dual redundant Bus Controller/Remote Terminal/Monitor  forming  MIL-STD-1553B      Notice-2. standard. Thus, the BISA-ISA-1553B is an excellent choice for dynamic real-time avionics simulations.

2.Design and development of 80386 based TCU/UHF & HF  hardware system for  electronic warfare system for DRDO Labs.

Courses Taught Previously(Odd & Even Semesters)

 Courses taught (2019-20 & 2020-21)

 INTERNATIONAL  JOURNAL PUBLICATIONS

1. S.Karthik Sai Ram,P.Muralidhar "A motion estimation based algorithm for encoding time reduction in  HEVC" Defence Science Journal, Vol. 72, No. 1, January 2022, pp. 56-66, DOI : 10.14429/dsj.72.16733(SCI)
2. Raveendra Podeti , Patri Sreehari Rao, P. Muralidhar "Highly reliable XoR Feed Arbiter Physical Unclonable Function (XFAPUF) in
   180 nm process for IoT security" Microprocessors and Microsystems 87 (2021) 104355 https://doi.org/10.1016/j.micpro.2021.104355(SCI)
3. S.Karthik Sai Ram,P.Muralidhar "Fast motion estimation in HEVC using horizontal subsampling and raster skip method"ETRI Journal(SCI) ,2020,Under Review
4. S.Karthik Sai Ram,P.Muralidhar "A Deep learning approach in SHVC for fast CU size decision" Displays Journal(SCI),2020,Under Review
5. S.Karthik Sai Ram,P.Muralidhar "Fast convolutional neural network based coding unit size prediction in HEVC",Journal of Signal Processing Systems(SCI),2020,Communicated
6. P.Muralidhar, C.B.RamaRao“Efficient Architecture for Global Elimination Algorithm for H.264  Motion Estimation” Sadhana - Vol. 41, No. 1, January 2016, pp. 47–54 Indian Academy of Sciences, Springer Publisher (SCI).
7. P.Muralidhar, C.B.RamaRao “High-performance Architecture of Motion Estimation algorithm for video compression.” Journal of circuits and systems Vol. 25, No. 8 (2016) 1650083 (15 pages) world scientific publishing company.(SCI)
8.  P.Muralidhar, C.B.RamaRao “Complexity reduction of fast block matching algorithm”  was published in the    International Journal of Engineering and Advanced Technology Volume 1/6, page Nos. 277-281, August 2012 
9.  P.Muralidhar, C.B.RamaRao “High performance Architecture for Full-search Block matching   algorithm” IOSR Journal of VLSI and Signal Processing(IOSR-JVSP) Vol. 5, Issue 1, Ver.II(Jan-Feb.2015) pp 41-49
10.  Vimal kumar, P.Muralidhar,C.B.Rama Rao, “Architecture for H.264 Intra prediction fast mode decision algorithm”,International journal of Computer Applications(0975-8887),Vol-68,No-3,April 2013 Scopus Indexed
11.  P.Muralidhar, C.B.Rama Rao, CYN.Dwith,, “Efficient Architecture for variable block size motion estimation in H.264/SVC  ACEEE International Journal on Signal & Image  Processing is published by ACEEE,USA ISSN 2152-5048 (print) ; ISSN 2152-5056 (online) ,2014  ,Vol.5. Issue: 1 pages (76-84)
12. K.Srinivasa chaitanya, P.Muralidhar,C.B.Rama Rao “Implementation of cordic based architecture for WCDMA/OFDM receiver” European Journal of Scientific Research ISSN   1450-216X Vol.36 No.1 (2009), pp.65-78 Scopus Indexed
13. Mangapathi Narendra Reddy,P.Muralidhar,C.B.Rama Rao “Design and implementation of custom processor architecture for turbo encoder and decoder using NISC” European Journal  of Scientific Research ISSN 1450-216X Vol.36 No.1 (2009), pp.79-92 Scopus Indexed

INTERNATIONAL CONFERENCE PUBLICATIONS:

1. B.B.Shabarinath,P.Muralidhar “Custom-IP for Gradient Descent Optimization based on Hardware/Software Co-design Paradigm” in the 24 th International Symposium on VLSI Design and Test (VDAT-2020) organized by IIT Bhubaneswar.
2. S.Karthik Sai Ram,P.Muralidhar,"Hybrid Fast Motion Estimation for HEVC",6th International Conference on Signal Processing and Integrated Networks (SPIN),2019
3. S.Karthik Sai Ram,P.Muralidhar,"Fast encoding in HEVC using subsampling with unsymmetrical octagonal search pattern",IEEE 16th India Council International Conference (INDICON),2019
4. S.Karthik Sai Ram,P.Muralidhar,"Fast Encoding using X-Search Pattern and Coded Block Flag Fast Method" First International Conference  Communications, Signal Processing and VLSI (IC2SV 2019)  held at the National Institute of Technology Warangal,2019
5. P.Muralidhar, C.B.Rama Rao, Gaurav Srivastava “A High-throughput Diamond search Architecture with shift mechanism for 720p Motion Estimation” International Conference on Devices, Circuits and Communications (ICDCCOM-2014) Technical Sponsored by IEEE, Birla Institute of Technology, Mesra, Ranchi India, September 12-13,2014.
6. P.Muralidhar, C.B.RamaRao, I.Ranjithkumar “Efficient architecture for variable block size motion estimation of H.264 video encoder”2012 International Conference on Solid-State and Integrated Circuit (ICSIC 2012) March 17,18    IPCSIT vol. XX (2011) © (2011) IACSIT Press, Singapore
7. P.Muralidhar, C.B.RamaRao, “Analysis of block matching motion estimation algorithms” International Conference on Computing, Communications, and Networking Technologies (ICCCNT 2013). The ICCCNT 2013 is Co-Sponsored by the IEEE Computer Society (USA). Tiruchengode, Tamilnadu, India, July 4-6, 2013
8. An Efficient VLSI Architecture for Spiral Type Variable  Block Size Motion Estimation in H.264/AVC” International conference on  Computer science and Information Technology(CSIT 2011),24th-25th july,2011 Bangalore
9. An Efficient  Architecture  for H.264 Intra Prediction Mode Decision Algorithm” 10th WSEAS International Conference on ELECTRONICS, HARDWARE, WIRELESS and OPTICAL COMMUNICATIONS (EHAC '11) held at University of Cambridge, Cambridge, UK, February 20-22, 2011
10. HW/SW Co-design of Motion Estimation Architecture for Video Codec Using Soft-Core Processor” IEEE Tencon Spring 2013 Sydney Australia 17-19 april,2013
11. “Modified full search block matching algorithm” International Conference on Computing, Communications and Networking Technologies (ICCCNT 2013). The ICCCNT 2013 is Co-Sponsored by the IEEE Computer Society(USA). Tamilnadu, India, July 4-6, 2013
12. “Architecture design of illumination change progressive motion estimation algorithm” International Conference on Computing, Communications and Networking Technologies (ICCCNT 2013). The ICCCNT 2013 is Co-Sponsored by the IEEE Computer Society (USA). Tamilnadu, India, July 4-6, 2013
13.  “New Fast search block matching motion estimation algorithm for H.264/AVC” International Conference on Recent Trends in Information Technology (ICRTIT 2014). Co-Sponsored by the IEEE Madras section, held at MIT Anna University Chennai, April 10^th -12^th   ,2014
14. “Edge Detection Based Block Matching Motion Estimation Algorithm for H.264/AVC ” International conference on  (ICPVS 2014) held at kakatiya university ,Warangal, India March,27-28,2014
15.  “Filtered Two-Bit Transform for Block Based Motion Estimation” 3^rd  International Conference on Signal Processing, Communication and Networking (ICSCN),2015. Technical sponsored by IEEE  held at MIT Anna University Chennai, March 26^th -28^th   ,2015
16.  “Symmetrical-cross Multi-Hexagon based Exhaustive Search for Block Motion Estimation” 3^rd  International Conference on Signal Processing, Communication and Networking (ICSCN),2015. Technical sponsored by IEEE  held at MIT Anna University Chennai, March 26^th -28^th  ,2015

Two Regular students and Two Part time students are Pursuing PhD

Faculty Development Programme (FDP)s   Organized

Co-Coordinator for 5 day GIAN program on, “Advanced CMOS Clock Generation Circuits” (Dec. 2017).

Outreach Activities

1. Delivered expert lecture in online STTP on “Applications of signal, image and video processing in VLSI using xilinx system generator” Phase1: 14^th -19^th ,September,2020 at Narayana Engineering college, Nellore
2. Delivered expert lecture in online STTP on “Applications of signal, image and video processing in VLSI using xilinx system generator” Phase2: 5^th -10^th Octobr,2020. At Narayana Engineering college, Nellore
3. Delivered expert lecture in online STTP on “Applications of signal, image and video processing in VLSI using xilinx system generator” Phase3: 26^th -31^stOctober,2020 at Narayana Engineering college, Nellore
4. External BOS Member for the department of ECE SR University, Warangal and participated in the BOS meeting held on 3^rd December,2020.
5. External examiner to evaluate the Ph.D. thesis "Low Power Sigma Delta Modulator Design using PVT Compensated Blocks" December,2019, JNTU Hyderabd
6. External examiner to evaluate the Ph.D. thesis " Development of Multi Class Classification Methods to Improve BCI Assistive Embedded System for Cognitive Disability", January,2020, JNTU Hyderabad
7. External examiner for final submission viva-voce examination of M.E. (ES&VLSID) programme on 30^th June,2021 Vasavi Engineering college, Hyderabad.
8. Participated in the BOS meeting of SR University,Warangal  on 22^nd ,July,2021

 DST/AICTE/MHRD or Other Sponsored  R&D Projects

1. "Advanced CMOS Clock generation  circuits"  MHRD sponsored SPARC project  in association

       with prof Pavan kumar Hanumolu,University of Illinois at Urbana Champaign 

               Amount               :            45 Lakhs

                Funding              :           MHRD under SPARC

               Role                       :          Co-Principal Investigator

               Status                  :           Under Progress

2. Multimedia and DSP Instruction set implementation for 32-bit Anupama Microprocessor

              Amount               :               9.5 Lakhs

               Funding               :   Defence Research & Development Organization (DRDO) under  Centre for acquisition of research services (CARS)     

               Role                      :                Co-Principal Investigator

               status                  :                 Completed

3.  Implementation of scalable video codec motion estimation algorithm on FPGA for multi   resolution video applications

                Amount               :               3.0 Lakhs

                Funding               :               Institute RSM grants

                Role                      :                Principal Investigator

                Status                 :                Completed

   Additional Responsibilities

Previous assignments

• III B.Tech course co-ordinator
• Dept.Time table in charge
• Dept. Teqip co-ordinator
• Dept.Training and Placement co-ordinator
• Dept Ph.D co-orinator

Institute Level:

• Warden , NIT Hostels for two years
• Associate Training and placement officer
• Faculty Advisor for EA & HAM student club
• Organized three student workshops under student club activity
• Assisted the organization of student Tech Fests by evaluating the H/W Projects of the Participants.
• Faculty In charge for Audio Visual Education Section