The programme is open to the faculty of engineering colleges, degree colleges, MCA colleges and other allied disciplines in India.
• ASIC Design Flow
• ASIC Implementation Routes
• Sources of Power Dissipation
• Low Power Design Techniques
• Data Path Elements:
Low power Adder Architectures
• Low Power Multiplier Architectures
• Low Power Logic Styles
• DSP Systems:
Representation of DSP Algorithms
• Loop bound and iteration bound
• Pipelining and parallel processing
for low power consumption
• Retiming, Unfolding, Folding
• Systolic Architecture Design
• ASIC Synthesis: Basics,
Timing Analysis and Constraints,
Static Timing Analysis
• Clock Tree Synthesis:
Clocks, Clock distributed Networks
• Routing: Deep sub-micron Issues,
crosstalk, Signal Integrity
• Programmable ASIC design:
Design Example using 7 series
FPGA device
Faculty and Research Scholars | Rs. 750/- |
Industry Participants | Rs. 2250/- |
Participants are required to fill the online registration form by clicking on the following link:
Registration Link:
https://forms.gle/JYGCEhqmMhV1QuNF7
Dr. B. Lakshmi
Associate Professor
Dept. of ECE,
National Institute of Technology
Warangal – 506004
Telangana, India
Mobile:
+919493436845
Email: lakshmi@nitw.ac.in
Registration Link:
https://forms.gle/JYGCEhqmMhV1QuNF7